1. Field of the Invention
The invention relates in general to a memory management technique, and more particularly, to a memory management technique for data packing.
2. Description of the Related Art
Recently, electronic products, such as digital cameras, video recorders, and smart phones, typically featured in capturing large-size and high-resolution images and videos attract consumers. Also, it is always a critical issue for hardware manufacturers to manufacture state-of-the-art image encoders of top quality, providing encoding and compression formats enabling a system to encode and decode information streams efficiently.
FIG. 1 shows a block diagram of a conventional image encoder. A pixel block input module 11 generates blocks with pixel data inputted at a data providing end. A converting/quantizing module 12 performs discrete cosine transform (DCT) and quantization on the blocks generated by the pixel block input module 11 to achieve a compression. Next, a run-length coding (RLC) module 13 identifies runs and lengths before the runs, and expresses the data content in the two paired parameters (run, length) to further compress the data amount. For example, quantized data 00000200007 may be expressed as (run, length)=(2, 5)(7, 4). A variable length coding (VLC) module 14 converts each set of the two paired parameters into an encoded bitstream according to a look-up table of the paired parameters outputted by the RLM 13. The length of the encoded bitstreams generated by the VLC module 14 may vary. A bitstream packing module 15 merges the encoded bitstreams generated by the VLC module 14 into packets having appropriate lengths.
An example of the bitstream packing module 15 comprising two barrel shifters shall be provided below to explain a common bitstream packing mechanism known in the prior art. Referring to FIG. 2A, barrel shifters 15A and 15B are capable of accommodating a data length of 32 bits and providing a maximum shift amount of 32 bits, respectively. The bitstream packing module 15 receives a bitstream in each cycle. Referring to FIG. 2B, in a first cycle, a bitstream a having a length of 8 bits is first stored in the barrel shifter 15A and is aligned to the left. In a subsequent second cycle, a bitstream b having a length of 16 bits is inputted into the bitstream packing module 15. In order to place the bitstream b adjacent to the right of the bitstream a, the barrel shifter 15A shifts the bitstream b by 8 bits to the right when receiving the bitstream b.
In a third cycle, a bitstream c having a length of 24 bits is transmitted to the bitstream packing module 15. Since the barrel shifter 15A has no sufficient remaining capacity, the bitstream c is divided into bitstreams c1 and c2 having a length of 8 bits and 16 bits, respectively, which are then respectively stored in the barrel shifters 15A and 15B. Assume the packet length generated by the bitstream packing module 15 is fixed at 32 bits. At this point, the bitstreams a, b, and c1 in the barrel shifter 15A are enough for a packet to be generated. Therefore, in a fourth cycle, apart from receiving a new bitstream d, the bitstream packing module 15 serially merges the bitstreams a, b, and c1 to one packet and outputs the packet. Referring to FIG. 2B, the bitstream c2 is relocated to align to the left of the barrel shifter 15A, and the bitstream d (8 bits) is stored into a segment adjacent to the bitstream c2 in the barrel shifter 15A.
It can be seen from the above descriptions that, in order to correctly serial the bitstreams, each time when receiving a bitstream, the bitstream packing module 15 is mandated to selectively relocate the bitstream to a correct segment by barrel shifting. Taking FIG. 2B for example, a start position of the bitstream b needs to be the 9th bit from the left in the barrel shifter 15A in order to be located adjacent to the bitstream a, and so the bitstream b is shifted by 8 bits to the right. Similarly, a start position of the bitstream c needs to be the 25th bit from the left in order to be located adjacent to the bitstream b, and so the bitstream c is shifted by 24 bits to the right. In this example, a maximum shift amount of the barrel shifters is 32 bits, since the bitstream packing module is fixed at 32 bits.
With larger image size and higher image resolution, an average length of bitstreams has increased in recent years. For example, bitstreams in earlier days do not exceed 32 bits, whereas lengths of modern bitstreams are mostly longer than 32 bits. Further, in response to the expanding amount of image data, requirements to processing speeds of encoder hardware have also become significantly higher to encode the increased bitstreams. For example, if the VLC module 14 is required to process two sets of data in each cycle, the length of the bitstreams received by the bitstream packing module 15 in each cycle may possibly be longer than 32 bits. Correspondingly, the bitstream packing module 15 needs to provide a maximum shift amount greater than 32 bits within each cycle.
A barrel shifter having a maximum shift amount greater than 32 bits (e.g., 64 bits) is not difficult in implementation. However, time for completing the shift with an intuitive design gets longer as the shift amount increases. While processing a large amount of data, if the bitstream packing module 15 cannot fully cooperate with the speed at which the VLC module 14 generates bitstreams to successfully receive, shift, merge, and output the bitstreams, the bitstream packing module 15 likely becomes the bottleneck that drags down an overall speed of the image encoder.
Assuming the quantization level of the converting/quantizing module 12 is increased to reduce the amount of subsequent data, although the speed requirement on the bitstream packing module 15 is alleviated, image quality is sacrificed—such an approach is hardly an ideal solution.